| SDIO_IT_CCRCFAIL | Command response received (CRC check failed) interrupt mask |
| SDIO_IT_DCRCFAIL | Data block sent/received (CRC check failed) interrupt mask |
| SDIO_IT_CTIMEOUT | Command response timeout interrupt mask |
| SDIO_IT_DTIMEOUT | Data timeout interrupt mask |
| SDIO_IT_TXUNDERR | Transmit FIFO underrun error interrupt mask |
| SDIO_IT_RXOVERR | Received FIFO overrun error interrupt mask |
| SDIO_IT_CMDREND | Command response received (CRC check passed) interrupt mask |
| SDIO_IT_CMDSENT | Command sent (no response required) interrupt mask |
| SDIO_IT_DATAEND | Data end (data counter SDIDCOUNT is zero) interrupt mask |
| SDIO_IT_STBITERR | Start bit not detected on all data signals in wide bus mode interrupt mask |
| SDIO_IT_DBCKEND | Data block sent/received (CRC check passed) interrupt mask |
| SDIO_IT_CMDACT | Command transfer in progress interrupt mask |
| SDIO_IT_TXACT | Data transmit in progress interrupt mask |
| SDIO_IT_RXACT | Data receive in progress interrupt mask |
| SDIO_IT_TXFIFOBW | Transmit FIFO burst writable interrupt mask |
| SDIO_IT_RXFIFOBR | Receive FIFO burst readable interrupt mask. |
| SDIO_IT_TXFIFOF | Transmit FIFO full interrupt mask |
| SDIO_IT_RXFIFOF | Receive FIFO full interrupt mask. |
| SDIO_IT_TXFIFOE | Transmit FIFO empty interrupt mask |
| SDIO_IT_RXFIFOE | Receive FIFO empty interrupt mask |
| SDIO_IT_TXDAVL | Data available in transmit FIFO interrupt mask |
| SDIO_IT_RXDAVL | Data available in receive FIFO interrupt mask |
| SDIO_IT_SDIOIT | SDIO interrupt received interrupt mask |
| SDIO_IT_CEATAEND | CE-ATA command completion signal received for CMD61 |
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